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HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Features:
x x
IDT70V9269S/L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access - Commercial: 9/12/15ns (max.) Low-power operation - IDT70V9269S Active: 429mW (typ.) Standby: 3.3mW (typ.) - IDT70V9269L Active: 429mW (typ.) Standby: 1.32mW (typ.) Flow-through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features Dual chip enables allow for depth expansion without
x
x
x x
x
additional logic Full synchronous operation on both ports - 4ns setup to clock and 1ns hold on all Control, data, and address inputs - Data input, address, and control registers - Fast 9ns clock to data out in the Pipelined output mode - Self-timed write allows fast cycle time - 15ns cycle time, 66MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (0.3V) power supply Industrial temperature range (-40C to +85C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
UBL CE0L
1 0 0/1
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
b
a
1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O8L-I/O15L I/O Control I/O0L-I/O7L I/O Control
I/O8R-I/O15R I/O0R-I/O7R
A13L A0L CLKL CNTENL
CNTRSTL ADSL
A13R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR
ADSR CNTENR CNTRSTR
3752 drw 01
JANUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC 3752/6
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9269 is a high-speed 16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address in-puts provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9269 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 429mW of power.
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
A10R A11R A12R A13R N/C N/C N/C N/C LBR UBR CE0R CE1R CNTRSTR VCC GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R VCC VCC I/O11R
Pin Configuration(1,2,3)
N/C N/C N/C N/C A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VCC ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L N/C N/C N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9269PRF PK-128(4) 128-Pin TQFP Top View(5)
A10L A11L A12L A13L N/C N/C N/C N/C LBL UBL CE0L CE1L CNTRSTL VCC GND R/WL OEL FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L VCC GND I/O11L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O10R I/O9R GND N/C I/O8R N/C N/C I/O7R VCC I/O6R I/O5R I/O4R GND I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VCC N/C N/C I/O8L N/C VCC I/O9L I/O10L
3752 drw 02
NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A13L I/O0L - I/O15L CLKL UBL LBL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A13R I/O0R - I/O15R CLKR UBR LBR ADSR CNTENR CNTRSTR FT/PIPER VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Upper Byte Select Lower Byte Select Address Strobe Enable Counter Enable Counter Reset Flow-Through / Pipeline Power Ground
3752 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O8-15 High-Z High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z Lower Byte I/O0-7 High-Z High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Deselected-Power Down Deselected-Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
3752 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
Address X An An X Previous Address X X Ap Ap Addr Used 0 An Ap Ap + 1 CLK ADS X L(4) H H CNTEN X X H L
(5)
CNTRST L H H H
I/O(3) DI/O(0) DI/O(n) DI/O(p) DI/O(p+1)
MODE Counte r Reset to Address 0 External Address Loaded into Counter External Address Blocked--Counter disabled (Ap reused) Counter Enabled--Internal Address generation
3752 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V
3752 tbl 04
Recommend DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.2 -0.3
(1)
Typ. 3.3 0
____
Max. 3.6 0 VCC+0.3V 0.8
(2)
Unit V V V V
3752 tbl 05
NOTE: 1. Industrial temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VCC + 0.3V.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V
Capacitance(1) (TA = +25C, f = 1.0MHz)
Symbol CIN COUT(3) Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
3752 tbl 07
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
o
C C
o
mA
3752 tbl 06
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 0.3V.
6.42 4
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V 0.3V)
70V9269S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 3.6V, VIN = 0V to VCC CE = VIH or CE1 = VIL, VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___
70V9269L Min.
___
Max. 10 10 0.4
___
Max. 5 5 0.4
___
Unit A A V V
3752 tbl 08
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temperture and Supply Voltage Range(3,6,7) (VCC = 3.3V 0.3V)
70V9269X9 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) Version COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. (4) 180 180
____ ____
70V9269X12 Com'l Only Typ.(4) 150 150
____ ____
70V9269X15 Com'l Only Typ.(4) 130 130
____ ____
Max. 260 225
____ ____
Max. 240 205
____ ____
Max. 220 185
____ ____
Unit mA
ISB1
CEL = CER = VIH f = fMAX
(1)
50 50
____ ____
75 65
____ ____
40 40
____ ____
65 50
____ ____
30 30
____ ____
55 35
____ ____
mA
ISB2
COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port, Outputs Disable d, f = fMAX(1) COM'L IND COM'L IND
110 110
____ ____
170 150
____ ____
100 100
____ ____
160 140
____ ____
90 90
____ ____
150 130
____ ____
mA
ISB3
1.0 0.4
____ ____
5 3
____ ____
1.0 0.4
____ ____
5 3
____ ____
1.0 0.4
____ ____
5 3
____ ____
mA
ISB4
100 100
____ ____
160 140
____ ____
90 90
____ ____
150 130
____ ____
80 80
____ ____
140 120
____ ____
mA
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 3.3V, TA = 25C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V 'X' represents "L" for left port or "R" for right port. 6. 'X' in part number indicates power rating (S or L). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3752 tbl 09
6.42 5
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1, 2, and 3
3752 tbl 10
3.3V 590 DATAOUT 435 30pF DATAOUT 435
3.3V
590
5pF*
3752 drw 03
3752 drw 04
Figure 1. AC Output Test load.
Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig.
8 7 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1
- 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
3752 drw 05
,
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42 6
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Tempurature Range (Read and Write Cycle Timing)(3,4,5) (VCC = 3.3V 0.3v, TA = 0C to +70C)
70V9269X9 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined)
(2) (2)
70V9269X12 Com'l Only Min. 30 20 12 12 8 8
____ ____
70V9269X15 Com'l Only Min. 35 25 12 12 10 10
____ ____
Parameter
(2)
Min. 25 15 12 12 6 6
____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined)
(2)
(2)
Clock Low Time (Pipelined)(2) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z
(1) (1) (2)
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
12
____
12
____
15
____
2 1
____ ____
2 1
____ ____
2 1
____ ____
Output Enable to Output High-Z
7 20 9
____
7 25 12
____
7 30 15
____
Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined)
(2)
Data Output Hold After Clock High Clock High to Output High-Z(1) Clock High to Output Low-Z(1)
2 2 2
2 2 2
2 2 2
9
____
9
____
9
____
Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time
____ ____
35 15
____ ____
40 15
____ ____
50 20
ns ns
70V9269 tbl 11
NOTES: 1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42 7
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-through Output on Either Port (FT/PIPEX = VIL)(3)
tCYC1 tCH1 CLK
CE0
tCL1
tSC CE1 tSB
UB, LB
tHC
tSC
(4)
tHC
tHB tSB tHB
R/W
tSW tSA
tHW tHA An + 1 tCD1 tDC Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2
An + 3 tCKHZ
(1)
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 2 tOLZ
(1)
tDC
OE
(2)
tOE
3752 drw 06
Timing Waveform of Read Cycle for Pipelined Operation on Either Port (FT/PIPEX = VIH)(3)
tCYC2 tCH2 CLK
CE0
tCL2
tSC CE1 tSB
UB, LB
tHC
tSC
(4)
tHC
tHB
tSB
(6)
tHB
R/W
tSW tSA
tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2 tDC Qn + 1
An + 3
DATAOUT
Qn + 2
(1)
(6)
tOHZ
tOLZ
(1)
OE
(2)
tOE
NOTES: 3752 drw 07 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6.42 8
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-device Pipelined Read(1,2)
tCH2 CLK tSA ADDRESS(B1) tSC
CE0(B1)
tCYC2 tCL2
tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC tCKHZ Q1 tDC A3 A4
(3)
A1
A2
A3
A4
A5
A6
tCD2 Q3 tCKLZ
(3)
DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1
tCKHZ (3) A5 A6
A2
tSC
CE0(B2)
tHC
tSC
tHC tCD2 tCKHZ(3) Q2 tCKLZ tCD2
(3)
DATAOUT(B2)
tCKLZ(3)
Q4
3752 drw 08
Timing Waveform of Left Port Write to Flow-through Right Port Read(4,5)
CLK L tSW R/W L tSA ADDRESS L tHA
NO MATCH
tHW
MATCH
tSD DATAIN L
tHD
VALID
tCCS CLK R
(6)
tCD1 R/W R tSW tSA ADDRESS R tHW tHA
NO MATCH
MATCH
tCWDD DATAOUT R tDC
(6)
tCD1
VALID VALID
tDC
3752 drw 09
NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V9269 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.42 9
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2 tCH2 tCL2 CLK
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W tSW tHW
ADDRESS
(4)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
DATAIN
(2)
tCD2 Qn READ
tCKHZ
(1)
tCKLZ
(1)
tCD2 Qn + 3
DATAOUT
NOP
(5)
WRITE
READ
3752 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2 CLK
CE0
tCYC2 tCL2
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W tSW tHW
ADDRESS DATAIN
(4)
An tSA tHA
An +1
An + 2 tSD tHD
An + 3
An + 4
An + 5
(2)
tCD2 Qn tOHZ(1)
Dn + 2
Dn + 3
tCKLZ(1)
tCD2 Qn + 4
DATAOUT
OE
READ
WRITE
READ
3752 drw 11
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 10
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-through Read-to-Write-to-Read (OE = VIL)(3)
tCH1 CLK tCYC1 tCL1
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W tSW tHW
ADDRESS
(4)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD
An + 3
An + 4
DATAIN
(2)
Dn + 2 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ (5) NOP
(1)
tCD1
tCD1 Qn + 3 tDC
3752 drw 12
DATAOUT
tCKLZ WRITE
(1)
READ
Timing Waveform of Flow-through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1 tCH1 tCL1 CLK
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W ADDRESS
(4)
tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2
(2)
An + 3
An + 4
An + 5
DATAIN tCD1 Qn tOHZ
OE
(1)
Dn + 3
tDC
tOE tCD1
(1)
tCD1 Qn + 4 tDC
DATAOUT
tCKLZ
READ
WRITE
READ
3752 drw 13
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or HIgh-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 11
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance (1)
tCH2 CLK tSA ADDRESS An tSAD tHAD
ADS
tCYC2 tCL2
tHA
tSAD tHAD
CNTEN
tSCN tHCN tCD2
DATAOUT
Qx - 1(2)
Qx tDC
Qn
Qn + 1
Qn + 2(2)
Qn + 3
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ WITH COUNTER
3752 drw 14
Timing Waveform of Flow-through Read with Address Counter Advance(1)
tCH1 CLK tSA ADDRESS An tSAD tHAD
ADS
tCYC1 tCL1
tHA
tSAD tHAD tSCN tHCN
CNTEN
tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
3752 drw 15
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address, i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks.
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IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) (1)
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
An
INTERNAL(3) ADDRESS tSAD tHAD
ADS
An(7)
An + 1
An + 2
An + 3
An + 4
CNTEN(7)
tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
3752 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2 CLK tSA tHA
(4)
tCYC2 tCL2
ADDRESS INTERNAL(3) ADDRESS R/W
ADS
An Ax
(6)
An + 1
An + 2
0 tSW tHW
1
An
An + 1
tSAD tHAD
CNTEN
tSCN tHCN tSRST tHRST
CNTRST
tSD
tHD D0
DATAIN
(5)
DATAOUT COUNTER RESET
(6)
Q0 WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n
Q1 READ ADDRESS n+1
Qn
NOTES: 3752 drw 17 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from `An' to `An + 1'. The transition show indicates the time required for the counter to advance. The `An +1' Address is written to during this cycle.
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IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
The IDT70V9269 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple Chip Enables allow easier banking of multiple IDT70V9269's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs.
Depth and Width Expansion
The IDT70V9269 features dual chip enables (refer to Truth Table 1) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V9269 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications.
A14
IDT70V9269
CE0 CE1 VCC
IDT70V9269
CE0 CE1 VCC
Control Inputs
Control Inputs
IDT70V9269
CE1 CE0
IDT70V9269
CE1 CE0 CNTRST CLK ADS CNTEN R/W LB, UB OE
Control Inputs
Control Inputs
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Figure 4. Depth and Width Expansion with IDT70V9269
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IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range
Blank I (1) PRF
Commercial (0C to +70C) Industrial (-40C to +85C) 128-pin TQFP (PK128-1)
9 12 15 S L
Commercial Only Commercial Only Commercial Only Standard Power Low Power
Speed in nanoseconds
70V9269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
3752 drw 19
Datasheet Document History
1/12/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth and Width Expansion section Page 4 Deleted note 6 for Table II Fixed Pin Configuration Replaced IDT logo Added FT/PIPE to left port Changed 200mV to 0mV in notes Page 4 Changed information in Truth Table II Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters-changed wording from "open" to "disabled" Removed Preliminary status
6/15/99: 8/20/99: 4/4/00:
1/17/01:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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